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authorWei Huang2017-02-10 18:40:28 +0100
committerPeter Maydell2017-02-10 18:40:28 +0100
commitfdb8665672ded05f650d18f8b62d5c8524b4385b (patch)
tree133faa75882fee6ca77cb4b0ad1b1b1b1aa58dff /target/arm/cpu.h
parenttarget-arm: Add support for PMU register PMSELR_EL0 (diff)
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target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0
In order to support Linux perf, which uses PMXEVTYPER register, this patch adds read/write access support for PMXEVTYPER. The access is CONSTRAINED UNPREDICTABLE when PMSELR is not 0x1f. Additionally this patch adds support for PMXEVTYPER_EL0. Signed-off-by: Wei Huang <wei@redhat.com> Message-id: 1486504171-26807-3-git-send-email-wei@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 7e609f7a99..edc1f761ce 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -307,7 +307,6 @@ typedef struct CPUARMState {
uint64_t c9_pmcr; /* performance monitor control register */
uint64_t c9_pmcnten; /* perf monitor counter enables */
uint32_t c9_pmovsr; /* perf monitor overflow status */
- uint32_t c9_pmxevtyper; /* perf monitor event type */
uint32_t c9_pmuserenr; /* perf monitor user enable */
uint64_t c9_pmselr; /* perf monitor counter selection register */
uint32_t c9_pminten; /* perf monitor interrupt enables */