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| author | Peter Maydell | 2017-09-12 20:13:55 +0200 |
|---|---|---|
| committer | Peter Maydell | 2017-09-21 17:31:09 +0200 |
| commit | ff96c64aec91fa2abc134347ad032c50376a6462 (patch) | |
| tree | f3b5ff0925c76f25d4c047ec37e09bc6d2cf2337 /target/arm/cpu.h | |
| parent | nvic: Implement NVIC_ITNS<n> registers (diff) | |
| download | qemu-ff96c64aec91fa2abc134347ad032c50376a6462.tar.gz qemu-ff96c64aec91fa2abc134347ad032c50376a6462.tar.xz qemu-ff96c64aec91fa2abc134347ad032c50376a6462.zip | |
nvic: Handle banked exceptions in nvic_recompute_state()
Update the nvic_recompute_state() code to handle the security
extension and its associated banked registers.
Code that uses the resulting cached state (ie the irq
acknowledge and complete code) will be updated in a later
commit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1505240046-11454-9-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
0 files changed, 0 insertions, 0 deletions