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| author | Claudio Fontana | 2021-02-04 17:39:23 +0100 |
|---|---|---|
| committer | Richard Henderson | 2021-02-05 21:24:15 +0100 |
| commit | 78271684719f34c1cc19f895e089f2f19b69698d (patch) | |
| tree | 5f47406eb8c2be4e37e411e5053678e4d91e09d3 /target/arm/cpu64.c | |
| parent | cpu: move debug_check_watchpoint to tcg_ops (diff) | |
| download | qemu-78271684719f34c1cc19f895e089f2f19b69698d.tar.gz qemu-78271684719f34c1cc19f895e089f2f19b69698d.tar.xz qemu-78271684719f34c1cc19f895e089f2f19b69698d.zip | |
cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass
we cannot in principle make the TCG Operations field definitions
conditional on CONFIG_TCG in code that is included by both common_ss
and specific_ss modules.
Therefore, what we can do safely to restrict the TCG fields to TCG-only
builds, is to move all tcg cpu operations into a separate header file,
which is only included by TCG, target-specific code.
This leaves just a NULL pointer in the cpu.h for the non-TCG builds.
This also tidies up the code in all targets a bit, having all TCG cpu
operations neatly contained by a dedicated data struct.
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20210204163931.7358-16-cfontana@suse.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm/cpu64.c')
| -rw-r--r-- | target/arm/cpu64.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index a9a1cdb871..10c5118176 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -21,6 +21,9 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" +#ifdef CONFIG_TCG +#include "hw/core/tcg-cpu-ops.h" +#endif /* CONFIG_TCG */ #include "qemu/module.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" @@ -805,10 +808,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); -#ifdef CONFIG_TCG - cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt; -#endif /* CONFIG_TCG */ - cc->gdb_read_register = aarch64_cpu_gdb_read_register; cc->gdb_write_register = aarch64_cpu_gdb_write_register; cc->gdb_num_core_regs = 34; |