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| author | Richard Henderson | 2018-10-24 08:50:17 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-10-24 08:51:29 +0200 |
| commit | cd208a1c3923bc097ec55c5b207d79294ab0e719 (patch) | |
| tree | 4b37c973aca05a1ad316b350ef920c3200eb6656 /target/arm/cpu64.c | |
| parent | target/arm: Convert jazelle from feature bit to isar1 test (diff) | |
| download | qemu-cd208a1c3923bc097ec55c5b207d79294ab0e719.tar.gz qemu-cd208a1c3923bc097ec55c5b207d79294ab0e719.tar.xz qemu-cd208a1c3923bc097ec55c5b207d79294ab0e719.zip | |
target/arm: Convert sve from feature bit to aa64pfr0 test
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181016223115.24100-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu64.c')
| -rw-r--r-- | target/arm/cpu64.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eb5aba4870..0520a42196 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -318,6 +318,10 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); cpu->isar.id_aa64isar1 = t; + t = cpu->isar.id_aa64pfr0; + t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); + cpu->isar.id_aa64pfr0 = t; + /* Replicate the same data to the 32-bit id registers. */ u = cpu->isar.id_isar5; u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ @@ -340,7 +344,6 @@ static void aarch64_max_initfn(Object *obj) * present in either. */ set_feature(&cpu->env, ARM_FEATURE_V8_FP16); - set_feature(&cpu->env, ARM_FEATURE_SVE); /* For usermode -cpu max we can use a larger and more efficient DCZ * blocksize since we don't have to follow what the hardware does. */ |