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| author | Richard Henderson | 2021-05-25 03:03:09 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-05-25 17:01:44 +0200 |
| commit | e6eba6e532a5f19519d925c8f68da032537abcac (patch) | |
| tree | 1b948454d2264b3ee6594809241084480753ef98 /target/arm/helper-sve.h | |
| parent | target/arm: Implement SVE2 HISTCNT, HISTSEG (diff) | |
| download | qemu-e6eba6e532a5f19519d925c8f68da032537abcac.tar.gz qemu-e6eba6e532a5f19519d925c8f68da032537abcac.tar.xz qemu-e6eba6e532a5f19519d925c8f68da032537abcac.zip | |
target/arm: Implement SVE2 XAR
In addition, use the same vector generator interface for AdvSIMD.
This fixes a bug in which the AdvSIMD insn failed to clear the
high bits of the SVE register.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-44-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper-sve.h')
| -rw-r--r-- | target/arm/helper-sve.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 507a2fea8e..28b8f00201 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -2558,6 +2558,10 @@ DEF_HELPER_FLAGS_5(sve2_histcnt_d, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_4(sve2_histseg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_xar_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_xar_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_xar_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_6(sve2_faddp_zpzz_s, TCG_CALL_NO_RWG, |