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| author | Rémi Denis-Courmont | 2021-01-12 11:45:02 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-01-19 15:38:52 +0100 |
| commit | c4f060e89effd70ebdb23d3315495d33af377a09 (patch) | |
| tree | ea48a815261cc7af81a90983fea9827202651fc3 /target/arm/helper.c | |
| parent | target/arm: add ARMv8.4-SEL2 system registers (diff) | |
| download | qemu-c4f060e89effd70ebdb23d3315495d33af377a09.tar.gz qemu-c4f060e89effd70ebdb23d3315495d33af377a09.tar.xz qemu-c4f060e89effd70ebdb23d3315495d33af377a09.zip | |
target/arm: handle VMID change in secure state
The VTTBR write callback so far assumes that the underlying VM lies in
non-secure state. This handles the secure state scenario.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-10-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper.c')
| -rw-r--r-- | target/arm/helper.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 9a0b8c9aa0..f8c18ab6c0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4018,10 +4018,15 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, * the combined stage 1&2 tlbs (EL10_1 and EL10_0). */ if (raw_read(env, ri) != value) { - tlb_flush_by_mmuidx(cs, - ARMMMUIdxBit_E10_1 | - ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0); + uint16_t mask = ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0; + + if (arm_is_secure_below_el3(env)) { + mask >>= ARM_MMU_IDX_A_NS; + } + + tlb_flush_by_mmuidx(cs, mask); raw_write(env, ri, value); } } |