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author | Richard Henderson | 2020-02-08 13:58:06 +0100 |
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committer | Peter Maydell | 2020-02-13 15:14:54 +0100 |
commit | 140845111809cd6fd57ccde93867b48cc56ffc74 (patch) | |
tree | 2cc8b81184dfc9a861ffb6dd02f93b3f8c87c111 /target/arm/internals.h | |
parent | target/arm: Remove CPSR_RESERVED (diff) | |
download | qemu-140845111809cd6fd57ccde93867b48cc56ffc74.tar.gz qemu-140845111809cd6fd57ccde93867b48cc56ffc74.tar.xz qemu-140845111809cd6fd57ccde93867b48cc56ffc74.zip |
target/arm: Introduce aarch64_pstate_valid_mask
Use this along the exception return path, where we previously
accepted any values.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200208125816.14954-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/internals.h')
-rw-r--r-- | target/arm/internals.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target/arm/internals.h b/target/arm/internals.h index 0569c96fd9..034d98ad53 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1085,6 +1085,18 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, return valid; } +static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id) +{ + uint32_t valid; + + valid = PSTATE_M | PSTATE_DAIF | PSTATE_IL | PSTATE_SS | PSTATE_NZCV; + if (isar_feature_aa64_bti(id)) { + valid |= PSTATE_BTYPE; + } + + return valid; +} + /* * Parameters of a given virtual address, as extracted from the * translation control register (TCR) for a given regime. |