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author | Peter Maydell | 2020-11-19 22:56:08 +0100 |
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committer | Peter Maydell | 2020-12-10 12:44:56 +0100 |
commit | 3423fbf10427db7680d3237d4f62d8370052fca0 (patch) | |
tree | 99621df5d4d2033875f5b2c509db270ba477f92c /target/arm/m-nocp.decode | |
parent | target/arm: Implement v8.1M REVIDR register (diff) | |
download | qemu-3423fbf10427db7680d3237d4f62d8370052fca0.tar.gz qemu-3423fbf10427db7680d3237d4f62d8370052fca0.tar.xz qemu-3423fbf10427db7680d3237d4f62d8370052fca0.zip |
target/arm: Implement new v8.1M NOCP check for exception return
In v8.1M a new exception return check is added which may cause a NOCP
UsageFault (see rule R_XLTP): before we clear s0..s15 and the FPSCR
we must check whether access to CP10 from the Security state of the
returning exception is disabled; if it is then we must take a fault.
(Note that for our implementation CPPWR is always RAZ/WI and so can
never cause CP10 accesses to fail.)
The other v8.1M change to this register-clearing code is that if MVE
is implemented VPR must also be cleared, so add a TODO comment to
that effect.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-20-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/m-nocp.decode')
0 files changed, 0 insertions, 0 deletions