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| author | Peter Maydell | 2021-09-21 17:32:19 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-09-21 17:32:19 +0200 |
| commit | 81ceb36b965c9d5ed5b1eb0ed80e23705802de15 (patch) | |
| tree | 1469b4ccb263ac8f365a2cea9080d6d525cd97c2 /target/arm/machine.c | |
| parent | Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210920' int... (diff) | |
| parent | target/arm: Optimize MVE 1op-immediate insns (diff) | |
| download | qemu-81ceb36b965c9d5ed5b1eb0ed80e23705802de15.tar.gz qemu-81ceb36b965c9d5ed5b1eb0ed80e23705802de15.tar.xz qemu-81ceb36b965c9d5ed5b1eb0ed80e23705802de15.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210921' into staging
target-arm queue:
* Optimize codegen for MVE when predication not active
* hvf: Add Apple Silicon support
* hw/intc: Set GIC maintenance interrupt level to only 0 or 1
* Fix mishandling of MVE FPSCR.LTPSIZE reset for usermode emulator
* elf2dmp: Fix coverity nits
# gpg: Signature made Tue 21 Sep 2021 16:31:17 BST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* remotes/pmaydell/tags/pull-target-arm-20210921: (27 commits)
target/arm: Optimize MVE 1op-immediate insns
target/arm: Optimize MVE VSLI and VSRI
target/arm: Optimize MVE VSHLL and VMOVL
target/arm: Optimize MVE VSHL, VSHR immediate forms
target/arm: Optimize MVE VMVN
target/arm: Optimize MVE VDUP
target/arm: Optimize MVE VNEG, VABS
target/arm: Optimize MVE arithmetic ops
target/arm: Optimize MVE logic ops
target/arm: Add TB flag for "MVE insns not predicated"
target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration
target/arm: Avoid goto_tb if we're trying to exit to the main loop
hvf: arm: Add rudimentary PMC support
arm: Add Hypervisor.framework build target
hvf: arm: Implement PSCI handling
hvf: arm: Implement -cpu host
arm/hvf: Add a WFI handler
hvf: Add Apple Silicon support
hvf: Introduce hvf_arch_init() callback
hvf: Add execute to dirty log permission bitmap
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/machine.c')
| -rw-r--r-- | target/arm/machine.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/target/arm/machine.c b/target/arm/machine.c index 81e30de824..c74d8c3f4b 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -781,6 +781,19 @@ static int cpu_post_load(void *opaque, int version_id) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + /* + * TCG gen_update_fp_context() relies on the invariant that + * FPDSCR.LTPSIZE is constant 4 for M-profile with the LOB extension; + * forbid bogus incoming data with some other value. + */ + if (arm_feature(env, ARM_FEATURE_M) && cpu_isar_feature(aa32_lob, cpu)) { + if (extract32(env->v7m.fpdscr[M_REG_NS], + FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4 || + extract32(env->v7m.fpdscr[M_REG_S], + FPCR_LTPSIZE_SHIFT, FPCR_LTPSIZE_LENGTH) != 4) { + return -1; + } + } if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } |