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| author | Richard Henderson | 2018-05-18 18:48:09 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-05-18 18:48:09 +0200 |
| commit | 96f922ccccb08c7725c1276ac87697f5dff69edf (patch) | |
| tree | 183c88ba082c637f48741b7ae8e1d2cc5fcb4fab /target/arm/sve.decode | |
| parent | target/arm: Implement SVE Index Generation Group (diff) | |
| download | qemu-96f922ccccb08c7725c1276ac87697f5dff69edf.tar.gz qemu-96f922ccccb08c7725c1276ac87697f5dff69edf.tar.xz qemu-96f922ccccb08c7725c1276ac87697f5dff69edf.zip | |
target/arm: Implement SVE Stack Allocation Group
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/sve.decode')
| -rw-r--r-- | target/arm/sve.decode | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 4f9f64f5ab..9d5c061165 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -84,6 +84,9 @@ # One register operand, with governing predicate, vector element size @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz +# Two register operands with a 6-bit signed immediate. +@rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri + # Two register operand, one immediate operand, with predicate, # element size encoded as TSZHL. User must fill in imm. @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \ @@ -238,6 +241,15 @@ INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5 # SVE index generation (register start, register increment) INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm +### SVE Stack Allocation Group + +# SVE stack frame adjustment +ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6 +ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6 + +# SVE stack frame size +RDVL 00000100 101 11111 01010 imm:s6 rd:5 + ### SVE Predicate Logical Operations Group # SVE predicate logical operations |