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| author | Richard Henderson | 2018-05-18 18:48:08 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-05-18 18:48:08 +0200 |
| commit | fe7f8dfb2dd27d4ae4fe48ecc7350c254702a0b7 (patch) | |
| tree | 9c081c4335d975b588df51684a3385e74e17da45 /target/arm/sve.decode | |
| parent | target/arm: Implement SVE bitwise shift by vector (predicated) (diff) | |
| download | qemu-fe7f8dfb2dd27d4ae4fe48ecc7350c254702a0b7.tar.gz qemu-fe7f8dfb2dd27d4ae4fe48ecc7350c254702a0b7.tar.xz qemu-fe7f8dfb2dd27d4ae4fe48ecc7350c254702a0b7.zip | |
target/arm: Implement SVE bitwise shift by wide elements (predicated)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180516223007.10256-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/sve.decode')
| -rw-r--r-- | target/arm/sve.decode | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 8267963b6b..1de289e55d 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -157,6 +157,12 @@ ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR +# SVE bitwise shift by wide elements (predicated) +# Note these require size != 3. +ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm +LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm +LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm + ### SVE Logical - Unpredicated Group # SVE bitwise logical operations (unpredicated) |