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| author | Richard Henderson | 2022-07-08 17:15:24 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-07-11 14:43:51 +0200 |
| commit | 7dbfafc157290b52af6109b82b8398d10ef5c3b3 (patch) | |
| tree | e74929c5054c72d53d8cb33df5a338b122d4cc38 /target/arm/sve_helper.c | |
| parent | target/arm: Implement PSEL (diff) | |
| download | qemu-7dbfafc157290b52af6109b82b8398d10ef5c3b3.tar.gz qemu-7dbfafc157290b52af6109b82b8398d10ef5c3b3.tar.xz qemu-7dbfafc157290b52af6109b82b8398d10ef5c3b3.zip | |
target/arm: Implement REVD
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/sve_helper.c')
| -rw-r--r-- | target/arm/sve_helper.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index df16170469..d6f7ef94fe 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -931,6 +931,22 @@ DO_ZPZ_D(sve_revh_d, uint64_t, hswap64) DO_ZPZ_D(sve_revw_d, uint64_t, wswap64) +void HELPER(sme_revd_q)(void *vd, void *vn, void *vg, uint32_t desc) +{ + intptr_t i, opr_sz = simd_oprsz(desc) / 8; + uint64_t *d = vd, *n = vn; + uint8_t *pg = vg; + + for (i = 0; i < opr_sz; i += 2) { + if (pg[H1(i)] & 1) { + uint64_t n0 = n[i + 0]; + uint64_t n1 = n[i + 1]; + d[i + 0] = n1; + d[i + 1] = n0; + } + } +} + DO_ZPZ(sve_rbit_b, uint8_t, H1, revbit8) DO_ZPZ(sve_rbit_h, uint16_t, H1_2, revbit16) DO_ZPZ(sve_rbit_s, uint32_t, H1_4, revbit32) |