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| author | Richard Henderson | 2019-09-04 21:30:05 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-09-05 14:23:03 +0200 |
| commit | 4ed95abd700e43dee8e032f754b53bec2b047f75 (patch) | |
| tree | 26c06cbe00c833de54c161b9e8def7975a24b1e1 /target/arm/t32.decode | |
| parent | target/arm: Convert Cyclic Redundancy Check (diff) | |
| download | qemu-4ed95abd700e43dee8e032f754b53bec2b047f75.tar.gz qemu-4ed95abd700e43dee8e032f754b53bec2b047f75.tar.xz qemu-4ed95abd700e43dee8e032f754b53bec2b047f75.zip | |
target/arm: Convert BX, BXJ, BLX (register)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190904193059.26202-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/t32.decode')
| -rw-r--r-- | target/arm/t32.decode | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 261db100ff..337706ebbe 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -26,6 +26,7 @@ &s_rrrr !extern s rd rn rm ra &rrrr !extern rd rn rm ra &rrr !extern rd rn rm +&r !extern rm &msr_reg !extern rn r mask &mrs_reg !extern rd r &msr_bank !extern rn r sysm @@ -211,4 +212,5 @@ CRC32CW 1111 1010 1101 .... 1111 .... 1010 .... @rndm MSR_reg 1111 0011 100 r:1 rn:4 1000 mask:4 0000 0000 &msr_reg MSR_v7m 1111 0011 100 0 rn:4 1000 mask:2 00 sysm:8 } + BXJ 1111 0011 1100 rm:4 1000 1111 0000 0000 &r } |