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| author | Richard Henderson | 2020-06-26 05:31:40 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-06-26 15:31:12 +0200 |
| commit | 337a03f07ff0f9e6295662f4094e03a045b60bdc (patch) | |
| tree | 92c2f7fa41b7bcfd1eeff25fceff9f6d96b7e024 /target/arm/tlb_helper.c | |
| parent | target/arm: Always pass cacheattr to get_phys_addr (diff) | |
| download | qemu-337a03f07ff0f9e6295662f4094e03a045b60bdc.tar.gz qemu-337a03f07ff0f9e6295662f4094e03a045b60bdc.tar.xz qemu-337a03f07ff0f9e6295662f4094e03a045b60bdc.zip | |
target/arm: Cache the Tagged bit for a page in MemTxAttrs
This "bit" is a particular value of the page's MemAttr.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-43-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/tlb_helper.c')
| -rw-r--r-- | target/arm/tlb_helper.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index 89d90465a3..b35dc8a011 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -188,6 +188,11 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size, phys_addr &= TARGET_PAGE_MASK; address &= TARGET_PAGE_MASK; } + /* Notice and record tagged memory. */ + if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs == 0xf0) { + arm_tlb_mte_tagged(&attrs) = true; + } + tlb_set_page_with_attrs(cs, address, phys_addr, attrs, prot, mmu_idx, page_size); return true; |