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| author | Richard Henderson | 2018-01-25 12:45:29 +0100 |
|---|---|---|
| committer | Peter Maydell | 2018-01-25 12:45:29 +0100 |
| commit | 9a2b5256ea1f68c89d5da4b54f180f576c2c82d6 (patch) | |
| tree | 19c1c44a16c7fb249a2bfb1e23e06fe0794e699a /target/arm/translate-a64.c | |
| parent | target/arm: Change the type of vfp.regs (diff) | |
| download | qemu-9a2b5256ea1f68c89d5da4b54f180f576c2c82d6.tar.gz qemu-9a2b5256ea1f68c89d5da4b54f180f576c2c82d6.tar.xz qemu-9a2b5256ea1f68c89d5da4b54f180f576c2c82d6.zip | |
target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers
Helpers that return a pointer into env->vfp.regs so that we isolate
the logic of how to index the regs array for different cpu modes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180119045438.28582-7-richard.henderson@linaro.org
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.c')
| -rw-r--r-- | target/arm/translate-a64.c | 25 |
1 files changed, 8 insertions, 17 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c14fb4185c..eed64c73e5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -164,15 +164,12 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, if (flags & CPU_DUMP_FPU) { int numvfpregs = 32; - for (i = 0; i < numvfpregs; i += 2) { - uint64_t vlo = env->vfp.regs[i * 2]; - uint64_t vhi = env->vfp.regs[(i * 2) + 1]; - cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ", - i, vhi, vlo); - vlo = env->vfp.regs[(i + 1) * 2]; - vhi = env->vfp.regs[((i + 1) * 2) + 1]; - cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n", - i + 1, vhi, vlo); + for (i = 0; i < numvfpregs; i++) { + uint64_t *q = aa64_vfp_qreg(env, i); + uint64_t vlo = q[0]; + uint64_t vhi = q[1]; + cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "%c", + i, vhi, vlo, (i & 1 ? '\n' : ' ')); } cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n", vfp_get_fpcr(env), vfp_get_fpsr(env)); @@ -558,19 +555,13 @@ static TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno) */ static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size) { - int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); -#ifdef HOST_WORDS_BIGENDIAN - offs += (8 - (1 << size)); -#endif - assert_fp_access_checked(s); - return offs; + return vec_reg_offset(s, regno, 0, size); } /* Offset of the high half of the 128 bit vector Qn */ static inline int fp_reg_hi_offset(DisasContext *s, int regno) { - assert_fp_access_checked(s); - return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]); + return vec_reg_offset(s, regno, 1, MO_64); } /* Convenience accessors for reading and writing single and double |