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| author | Richard Henderson | 2018-08-16 15:05:29 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-08-16 15:29:58 +0200 |
| commit | b8a4a96db3639e17ab5e5cdc14fca4b19fbf5b3b (patch) | |
| tree | 4bc506b48e861e58a2d406a1ff6125abd0b7c7ec /target/arm/translate-a64.c | |
| parent | target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half (diff) | |
| download | qemu-b8a4a96db3639e17ab5e5cdc14fca4b19fbf5b3b.tar.gz qemu-b8a4a96db3639e17ab5e5cdc14fca4b19fbf5b3b.tar.xz qemu-b8a4a96db3639e17ab5e5cdc14fca4b19fbf5b3b.zip | |
target/arm: Fix aa64 FCADD and FCMLA decode
These insns require u=1; failed to include that in the switch
cases. This probably happened during one of the rebases just
before final commit.
Fixes: d17b7cdcf4e
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20180810193129.1556-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.c')
| -rw-r--r-- | target/arm/translate-a64.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b29dc49c4f..8ca3876707 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11423,12 +11423,12 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn) } feature = ARM_FEATURE_V8_DOTPROD; break; - case 0x8: /* FCMLA, #0 */ - case 0x9: /* FCMLA, #90 */ - case 0xa: /* FCMLA, #180 */ - case 0xb: /* FCMLA, #270 */ - case 0xc: /* FCADD, #90 */ - case 0xe: /* FCADD, #270 */ + case 0x18: /* FCMLA, #0 */ + case 0x19: /* FCMLA, #90 */ + case 0x1a: /* FCMLA, #180 */ + case 0x1b: /* FCMLA, #270 */ + case 0x1c: /* FCADD, #90 */ + case 0x1e: /* FCADD, #270 */ if (size == 0 || (size == 1 && !arm_dc_feature(s, ARM_FEATURE_V8_FP16)) || (size == 3 && !is_q)) { |