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| author | Peter Maydell | 2021-09-01 10:02:34 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-09-01 12:08:16 +0200 |
| commit | 1e35cd916695389074b12614d254087a9f51b852 (patch) | |
| tree | 7a7df092b27d80b64cf1ba986123c13a1913f583 /target/arm/translate-mve.c | |
| parent | hw: Add compat machines for 6.2 (diff) | |
| download | qemu-1e35cd916695389074b12614d254087a9f51b852.tar.gz qemu-1e35cd916695389074b12614d254087a9f51b852.tar.xz qemu-1e35cd916695389074b12614d254087a9f51b852.zip | |
target/arm: Implement MVE VADD (floating-point)
Implement the MVE VADD (floating-point) insn. Handling of this is
similar to the 2-operand integer insns, except that we must take care
to only update the floating point exception status if the least
significant bit of the predicate mask for each element is active.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-mve.c')
| -rw-r--r-- | target/arm/translate-mve.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 78229c44c6..d2c40ede56 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -831,6 +831,23 @@ static bool trans_VSBCI(DisasContext *s, arg_2op *a) return do_2op(s, a, gen_helper_mve_vsbci); } +#define DO_2OP_FP(INSN, FN) \ + static bool trans_##INSN(DisasContext *s, arg_2op *a) \ + { \ + static MVEGenTwoOpFn * const fns[] = { \ + NULL, \ + gen_helper_mve_##FN##h, \ + gen_helper_mve_##FN##s, \ + NULL, \ + }; \ + if (!dc_isar_feature(aa32_mve_fp, s)) { \ + return false; \ + } \ + return do_2op(s, a, fns[a->size]); \ + } + +DO_2OP_FP(VADD_fp, vfadd) + static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, MVEGenTwoOpScalarFn fn) { |