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| author | Peter Maydell | 2021-06-17 14:16:11 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-06-24 15:58:47 +0200 |
| commit | 39f2ec8592dd3c823034dc4decc64c7e4cc42bfd (patch) | |
| tree | e0d566b654bdb3220038ee5d7a90f94e36c007ec /target/arm/translate-mve.c | |
| parent | target/arm: Implement MVE VPST (diff) | |
| download | qemu-39f2ec8592dd3c823034dc4decc64c7e4cc42bfd.tar.gz qemu-39f2ec8592dd3c823034dc4decc64c7e4cc42bfd.tar.xz qemu-39f2ec8592dd3c823034dc4decc64c7e4cc42bfd.zip | |
target/arm: Implement MVE VQADD and VQSUB
Implement the MVE VQADD and VQSUB insns, which perform saturating
addition of a scalar to each element. Note that individual bytes of
each result element are used or discarded according to the predicate
mask, but FPSCR.QC is only set if the predicate mask for the lowest
byte of the element is set.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210617121628.20116-28-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/translate-mve.c')
| -rw-r--r-- | target/arm/translate-mve.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 7c4c06e434..27c69d9c7d 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -446,6 +446,10 @@ DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar) DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar) DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar) DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar) +DO_2OP_SCALAR(VQADD_S_scalar, vqadds_scalar) +DO_2OP_SCALAR(VQADD_U_scalar, vqaddu_scalar) +DO_2OP_SCALAR(VQSUB_S_scalar, vqsubs_scalar) +DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar) DO_2OP_SCALAR(VBRSR, vbrsr) static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, |