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| author | Richard Henderson | 2021-04-19 22:22:57 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-04-30 12:16:51 +0200 |
| commit | 0ca0f8720a424a643d33cce802a4b769fbb62836 (patch) | |
| tree | b8e8b621567f92a3c30463d3430603961fb8fe09 /target/arm/translate-sve.c | |
| parent | target/arm: Enforce alignment for aa64 vector LDn/STn (single) (diff) | |
| download | qemu-0ca0f8720a424a643d33cce802a4b769fbb62836.tar.gz qemu-0ca0f8720a424a643d33cce802a4b769fbb62836.tar.xz qemu-0ca0f8720a424a643d33cce802a4b769fbb62836.zip | |
target/arm: Enforce alignment for sve LD1R
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-32-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-sve.c')
| -rw-r--r-- | target/arm/translate-sve.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 584c4d047c..864ed669c4 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -5001,7 +5001,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a) clean_addr = gen_mte_check1(s, temp, false, true, msz); tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s), - s->be_data | dtype_mop[a->dtype]); + finalize_memop(s, dtype_mop[a->dtype])); /* Broadcast to *all* elements. */ tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd), |