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| author | Richard Henderson | 2018-08-16 15:05:29 +0200 |
|---|---|---|
| committer | Peter Maydell | 2018-08-16 15:29:58 +0200 |
| commit | e4ab5124a5c2e2291006b24bdc21c3dd8d087ff4 (patch) | |
| tree | 1a59c55f0bed820858cdae71df9d7fccd16341f7 /target/arm/translate-sve.c | |
| parent | target/arm: Use fp_status_fp16 for do_fmpa_zpzzz_h (diff) | |
| download | qemu-e4ab5124a5c2e2291006b24bdc21c3dd8d087ff4.tar.gz qemu-e4ab5124a5c2e2291006b24bdc21c3dd8d087ff4.tar.xz qemu-e4ab5124a5c2e2291006b24bdc21c3dd8d087ff4.zip | |
target/arm: Use FZ not FZ16 for SVE FCVT single-half and double-half
We were using the wrong flush-to-zero bit for the non-half input.
Fixes: 46d33d1e3c9
Cc: qemu-stable@nongnu.org (3.0.1)
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20180810193129.1556-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-sve.c')
| -rw-r--r-- | target/arm/translate-sve.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index d27bc8c946..667879564f 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4093,7 +4093,7 @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg, static bool trans_FCVT_sh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) { - return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_sh); + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_sh); } static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn) @@ -4103,7 +4103,7 @@ static bool trans_FCVT_hs(DisasContext *s, arg_rpr_esz *a, uint32_t insn) static bool trans_FCVT_dh(DisasContext *s, arg_rpr_esz *a, uint32_t insn) { - return do_zpz_ptr(s, a->rd, a->rn, a->pg, true, gen_helper_sve_fcvt_dh); + return do_zpz_ptr(s, a->rd, a->rn, a->pg, false, gen_helper_sve_fcvt_dh); } static bool trans_FCVT_hd(DisasContext *s, arg_rpr_esz *a, uint32_t insn) |