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authorRichard Henderson2020-11-02 17:52:14 +0100
committerPeter Maydell2020-11-02 17:52:14 +0100
commit4d5fa5a80ac28f34b8497be1e85371272413a12e (patch)
treea1b77a6f597e4718a6b9745d1ad9cccad074ae3f /target/arm/translate-vfp.c.inc
parenttarget/arm: Add read/write_neon_element32 (diff)
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target/arm: Expand read/write_neon_element32 to all MemOp
We can then use this to improve VMOV (scalar to gp) and VMOV (gp to scalar) so that we simply perform the memory operation that we wanted, rather than inserting or extracting from a 32-bit quantity. These were the last uses of neon_load/store_reg, so remove them. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20201030022618.785675-7-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-vfp.c.inc')
-rw-r--r--target/arm/translate-vfp.c.inc71
1 files changed, 9 insertions, 62 deletions
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index 368bae0a73..28f22f9872 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -511,11 +511,9 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
{
/* VMOV scalar to general purpose register */
TCGv_i32 tmp;
- int pass;
- uint32_t offset;
- /* SIZE == 2 is a VFP instruction; otherwise NEON. */
- if (a->size == 2
+ /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */
+ if (a->size == MO_32
? !dc_isar_feature(aa32_fpsp_v2, s)
: !arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false;
@@ -526,44 +524,12 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
return false;
}
- offset = a->index << a->size;
- pass = extract32(offset, 2, 1);
- offset = extract32(offset, 0, 2) * 8;
-
if (!vfp_access_check(s)) {
return true;
}
- tmp = neon_load_reg(a->vn, pass);
- switch (a->size) {
- case 0:
- if (offset) {
- tcg_gen_shri_i32(tmp, tmp, offset);
- }
- if (a->u) {
- gen_uxtb(tmp);
- } else {
- gen_sxtb(tmp);
- }
- break;
- case 1:
- if (a->u) {
- if (offset) {
- tcg_gen_shri_i32(tmp, tmp, 16);
- } else {
- gen_uxth(tmp);
- }
- } else {
- if (offset) {
- tcg_gen_sari_i32(tmp, tmp, 16);
- } else {
- gen_sxth(tmp);
- }
- }
- break;
- case 2:
- break;
- }
+ tmp = tcg_temp_new_i32();
+ read_neon_element32(tmp, a->vn, a->index, a->size | (a->u ? 0 : MO_SIGN));
store_reg(s, a->rt, tmp);
return true;
@@ -572,12 +538,10 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a)
static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
{
/* VMOV general purpose register to scalar */
- TCGv_i32 tmp, tmp2;
- int pass;
- uint32_t offset;
+ TCGv_i32 tmp;
- /* SIZE == 2 is a VFP instruction; otherwise NEON. */
- if (a->size == 2
+ /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */
+ if (a->size == MO_32
? !dc_isar_feature(aa32_fpsp_v2, s)
: !arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false;
@@ -588,30 +552,13 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a)
return false;
}
- offset = a->index << a->size;
- pass = extract32(offset, 2, 1);
- offset = extract32(offset, 0, 2) * 8;
-
if (!vfp_access_check(s)) {
return true;
}
tmp = load_reg(s, a->rt);
- switch (a->size) {
- case 0:
- tmp2 = neon_load_reg(a->vn, pass);
- tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 8);
- tcg_temp_free_i32(tmp2);
- break;
- case 1:
- tmp2 = neon_load_reg(a->vn, pass);
- tcg_gen_deposit_i32(tmp, tmp2, tmp, offset, 16);
- tcg_temp_free_i32(tmp2);
- break;
- case 2:
- break;
- }
- neon_store_reg(a->vn, pass, tmp);
+ write_neon_element32(tmp, a->vn, a->index, a->size);
+ tcg_temp_free_i32(tmp);
return true;
}