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author | Richard Henderson | 2020-02-24 23:22:24 +0100 |
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committer | Peter Maydell | 2020-02-28 17:14:57 +0100 |
commit | c52881bbc22b50db99a6c37171ad3eea7d959ae6 (patch) | |
tree | 5fee296b9c6e8422f19bb2182d88401ce338f768 /target/arm/translate-vfp.inc.c | |
parent | target/arm: Add missing checks for fpsp_v2 (diff) | |
download | qemu-c52881bbc22b50db99a6c37171ad3eea7d959ae6.tar.gz qemu-c52881bbc22b50db99a6c37171ad3eea7d959ae6.tar.xz qemu-c52881bbc22b50db99a6c37171ad3eea7d959ae6.zip |
target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac
All remaining tests for VFP4 are for fused multiply-add insns.
Since the MVFR1 field is used for both VFP and NEON, move its adjustment
from the !has_neon block to the (!has_vfp && !has_neon) block.
Test for vfp of the appropraite width alongside the test for simdfmac
within translate-vfp.inc.c. Within disas_neon_data_insn, we have
already tested for ARM_FEATURE_NEON.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200224222232.13807-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-vfp.inc.c')
-rw-r--r-- | target/arm/translate-vfp.inc.c | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index f88a95438f..03ba8d7aac 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1803,11 +1803,18 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a) /* * Present in VFPv4 only. + * Note that we can't rely on the SIMDFMAC check alone, because + * in a Neon-no-VFP core that ID register field will be non-zero. + */ + if (!dc_isar_feature(aa32_simdfmac, s) || + !dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* * In v7A, UNPREDICTABLE with non-zero vector length/stride; from * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || - (s->vec_len != 0 || s->vec_stride != 0)) { + if (s->vec_len != 0 || s->vec_stride != 0) { return false; } @@ -1861,11 +1868,18 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a) /* * Present in VFPv4 only. + * Note that we can't rely on the SIMDFMAC check alone, because + * in a Neon-no-VFP core that ID register field will be non-zero. + */ + if (!dc_isar_feature(aa32_simdfmac, s) || + !dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + /* * In v7A, UNPREDICTABLE with non-zero vector length/stride; from * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || - (s->vec_len != 0 || s->vec_stride != 0)) { + if (s->vec_len != 0 || s->vec_stride != 0) { return false; } |