diff options
| author | Richard Henderson | 2021-04-19 22:22:45 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-04-30 12:16:51 +0200 |
| commit | 2fd0800c68b48c5402eea0f88bd68aadfdc15004 (patch) | |
| tree | 593c5d9a28b6ba4ff6d4c639dd730dc598e69480 /target/arm/translate.c | |
| parent | target/arm: Enforce alignment for RFE (diff) | |
| download | qemu-2fd0800c68b48c5402eea0f88bd68aadfdc15004.tar.gz qemu-2fd0800c68b48c5402eea0f88bd68aadfdc15004.tar.xz qemu-2fd0800c68b48c5402eea0f88bd68aadfdc15004.zip | |
target/arm: Enforce alignment for SRS
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.c')
| -rw-r--r-- | target/arm/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index b8704d2504..3b071012ca 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5200,11 +5200,11 @@ static void gen_srs(DisasContext *s, } tcg_gen_addi_i32(addr, addr, offset); tmp = load_reg(s, 14); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); tmp = load_cpu_field(spsr); tcg_gen_addi_i32(addr, addr, 4); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN); tcg_temp_free_i32(tmp); if (writeback) { switch (amode) { |