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authorRichard Henderson2021-04-19 22:22:31 +0200
committerPeter Maydell2021-04-30 12:16:50 +0200
commit3902bfc6f06144016b8b25f5b6fb2211e85406fc (patch)
treee450ea5f49be678d07ab3595763e8a1ea72a9dec /target/arm/translate.c
parenttarget/arm: Add wrapper macros for accessing tbflags (diff)
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target/arm: Introduce CPUARMTBFlags
In preparation for splitting tb->flags across multiple fields, introduce a structure to hold the value(s). So far this only migrates the one uint32_t and fixes all of the places that require adjustment to match. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210419202257.161730-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.c')
-rw-r--r--target/arm/translate.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 5c21e98d24..6a15e5d16c 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8852,7 +8852,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUARMState *env = cs->env_ptr;
ARMCPU *cpu = env_archcpu(env);
- uint32_t tb_flags = dc->base.tb->flags;
+ CPUARMTBFlags tb_flags = arm_tbflags_from_tb(dc->base.tb);
uint32_t condexec, core_mmu_idx;
dc->isar = &cpu->isar;
@@ -9359,12 +9359,13 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
{
DisasContext dc = { };
const TranslatorOps *ops = &arm_translator_ops;
+ CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb);
- if (EX_TBFLAG_AM32(tb->flags, THUMB)) {
+ if (EX_TBFLAG_AM32(tb_flags, THUMB)) {
ops = &thumb_translator_ops;
}
#ifdef TARGET_AARCH64
- if (EX_TBFLAG_ANY(tb->flags, AARCH64_STATE)) {
+ if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) {
ops = &aarch64_translator_ops;
}
#endif