diff options
| author | Richard Henderson | 2021-04-19 22:22:36 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-04-30 12:16:50 +0200 |
| commit | 4479ec30c9c4d2399b6e5bf4e77d136cfd27aebd (patch) | |
| tree | f4c8888291f69d3bbeeb17887498b85ab56dcf28 /target/arm/translate.c | |
| parent | target/arm: Move TBFLAG_ANY bits to the bottom (diff) | |
| download | qemu-4479ec30c9c4d2399b6e5bf4e77d136cfd27aebd.tar.gz qemu-4479ec30c9c4d2399b6e5bf4e77d136cfd27aebd.tar.xz qemu-4479ec30c9c4d2399b6e5bf4e77d136cfd27aebd.zip | |
target/arm: Add ALIGN_MEM to TBFLAG_ANY
Use this to signal when memory access alignment is required.
This value comes from the CCR register for M-profile, and
from the SCTLR register for A-profile.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210419202257.161730-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.c')
| -rw-r--r-- | target/arm/translate.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index 6a15e5d16c..970e537eae 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -933,8 +933,7 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, { TCGv addr; - if (arm_dc_feature(s, ARM_FEATURE_M) && - !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) { + if (s->align_mem) { opc |= MO_ALIGN; } @@ -948,8 +947,7 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32, { TCGv addr; - if (arm_dc_feature(s, ARM_FEATURE_M) && - !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) { + if (s->align_mem) { opc |= MO_ALIGN; } @@ -8877,6 +8875,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) dc->user = (dc->current_el == 0); #endif dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL); + dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM); if (arm_feature(env, ARM_FEATURE_M)) { dc->vfp_enabled = 1; |