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| author | Peter Maydell | 2021-07-30 17:16:36 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-08-25 11:48:50 +0200 |
| commit | e5346292966f5348cd36668f2451ca0e44d820b2 (patch) | |
| tree | 8edd319248d5af1846e528cc6c98f0342a00cdf3 /target/arm/translate.c | |
| parent | target/arm: Re-indent sdiv and udiv helpers (diff) | |
| download | qemu-e5346292966f5348cd36668f2451ca0e44d820b2.tar.gz qemu-e5346292966f5348cd36668f2451ca0e44d820b2.tar.xz qemu-e5346292966f5348cd36668f2451ca0e44d820b2.zip | |
target/arm: Implement M-profile trapping on division by zero
Unlike A-profile, for M-profile the UDIV and SDIV insns can be
configured to raise an exception on division by zero, using the CCR
DIV_0_TRP bit.
Implement support for setting this bit by making the helper functions
raise the appropriate exception.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210730151636.17254-3-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/translate.c')
| -rw-r--r-- | target/arm/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index 804a53279b..115aa768b6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7992,9 +7992,9 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool u) t1 = load_reg(s, a->rn); t2 = load_reg(s, a->rm); if (u) { - gen_helper_udiv(t1, t1, t2); + gen_helper_udiv(t1, cpu_env, t1, t2); } else { - gen_helper_sdiv(t1, t1, t2); + gen_helper_sdiv(t1, cpu_env, t1, t2); } tcg_temp_free_i32(t2); store_reg(s, a->rd, t1); |