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authorRichard Henderson2020-04-18 18:28:08 +0200
committerPeter Maydell2020-04-30 16:35:41 +0200
commit6b375d3546b009d1e63e07397ec9c6af256e15e9 (patch)
tree0e8404b6fb1e88f8da168b8468378753bf619b4a /target/arm/translate.h
parentnet: cadence_gem: clear RX control descriptor (diff)
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target/arm: Vectorize integer comparison vs zero
These instructions are often used in glibc's string routines. They were the final uses of the 32-bit at a time neon helpers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200418162808.4680-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate.h')
-rw-r--r--target/arm/translate.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/translate.h b/target/arm/translate.h
index d9ea0c99cc..98b319f3f6 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -275,6 +275,11 @@ static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
uint64_t vfp_expand_imm(int size, uint8_t imm8);
/* Vector operations shared between ARM and AArch64. */
+extern const GVecGen2 ceq0_op[4];
+extern const GVecGen2 clt0_op[4];
+extern const GVecGen2 cgt0_op[4];
+extern const GVecGen2 cle0_op[4];
+extern const GVecGen2 cge0_op[4];
extern const GVecGen3 mla_op[4];
extern const GVecGen3 mls_op[4];
extern const GVecGen3 cmtst_op[4];