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| author | Peter Maydell | 2020-08-28 20:33:32 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-09-01 12:19:32 +0200 |
| commit | e4a6d4a69e239becfd83bdcd996476e7b8e1138d (patch) | |
| tree | 21431394aad0edec16f00c7ec88302a6fcbc8c6a /target/arm/vec_helper.c | |
| parent | target/arm: Implement VFP fp16 VMOV between gp and halfprec registers (diff) | |
| download | qemu-e4a6d4a69e239becfd83bdcd996476e7b8e1138d.tar.gz qemu-e4a6d4a69e239becfd83bdcd996476e7b8e1138d.tar.xz qemu-e4a6d4a69e239becfd83bdcd996476e7b8e1138d.zip | |
target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL
Implement FP16 support for the Neon insns which use the DO_3S_FP_GVEC
macro: VADD, VSUB, VABD, VMUL.
For VABD this requires us to implement a new gvec_fabd_h helper
using the machinery we have already for the other helpers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-24-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/vec_helper.c')
| -rw-r--r-- | target/arm/vec_helper.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index a6c53d2ab6..988d5784e8 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -707,6 +707,11 @@ static float64 float64_ftsmul(float64 op1, uint64_t op2, float_status *stat) return result; } +static float16 float16_abd(float16 op1, float16 op2, float_status *stat) +{ + return float16_abs(float16_sub(op1, op2, stat)); +} + static float32 float32_abd(float32 op1, float32 op2, float_status *stat) { return float32_abs(float32_sub(op1, op2, stat)); @@ -739,6 +744,7 @@ DO_3OP(gvec_ftsmul_h, float16_ftsmul, float16) DO_3OP(gvec_ftsmul_s, float32_ftsmul, float32) DO_3OP(gvec_ftsmul_d, float64_ftsmul, float64) +DO_3OP(gvec_fabd_h, float16_abd, float16) DO_3OP(gvec_fabd_s, float32_abd, float32) #ifdef TARGET_AARCH64 |