diff options
| author | Richard Henderson | 2022-10-11 05:18:53 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-10-20 12:27:49 +0200 |
| commit | 00b20ee42ea97f2329779851a7f8a290712109ee (patch) | |
| tree | a08a8a11bfacd17162dacf6763a5101df11fa3cf /target/arm | |
| parent | target/arm: Move ARMMMUIdx_Stage2 to a real tlb mmu_idx (diff) | |
| download | qemu-00b20ee42ea97f2329779851a7f8a290712109ee.tar.gz qemu-00b20ee42ea97f2329779851a7f8a290712109ee.tar.xz qemu-00b20ee42ea97f2329779851a7f8a290712109ee.zip | |
target/arm: Restrict tlb flush from vttbr_write to vmid change
Compare only the VMID field when considering whether we need to flush.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221011031911.2408754-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/helper.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 18c51bb777..c672903f43 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3815,10 +3815,10 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, * A change in VMID to the stage2 page table (Stage2) invalidates * the stage2 and combined stage 1&2 tlbs (EL10_1 and EL10_0). */ - if (raw_read(env, ri) != value) { + if (extract64(raw_read(env, ri) ^ value, 48, 16) != 0) { tlb_flush_by_mmuidx(cs, alle1_tlbmask(env)); - raw_write(env, ri, value); } + raw_write(env, ri, value); } static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { |