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| author | Rebecca Cran | 2021-02-08 07:56:59 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-02-11 12:50:14 +0100 |
| commit | 2bf1eff9e9125a3d73901991dcfb9cb2ace03be1 (patch) | |
| tree | 7fb22fa6d2eb20f4525105188b568b72f1bdb297 /target/arm | |
| parent | target/arm: Support AA32 DIT by moving PSTATE_SS from cpsr into env->pstate (diff) | |
| download | qemu-2bf1eff9e9125a3d73901991dcfb9cb2ace03be1.tar.gz qemu-2bf1eff9e9125a3d73901991dcfb9cb2ace03be1.tar.xz qemu-2bf1eff9e9125a3d73901991dcfb9cb2ace03be1.zip | |
target/arm: Set ID_AA64PFR0.DIT and ID_PFR0.DIT to 1 for "max" AA64 CPU
Enable FEAT_DIT for the "max" AARCH64 CPU.
Signed-off-by: Rebecca Cran <rebecca@nuviainc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210208065700.19454-4-rebecca@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/cpu64.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 10c5118176..c255f1bcc3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -669,6 +669,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64PFR0, FP, 1); t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); + t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); cpu->isar.id_aa64pfr0 = t; t = cpu->isar.id_aa64pfr1; @@ -718,6 +719,10 @@ static void aarch64_max_initfn(Object *obj) u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 = u; + u = cpu->isar.id_pfr0; + u = FIELD_DP32(u, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 = u; + u = cpu->isar.id_mmfr3; u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ cpu->isar.id_mmfr3 = u; |