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| author | Peter Maydell | 2021-09-13 11:54:36 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-09-21 17:28:27 +0200 |
| commit | 5cf525a8a68f5734feef8899d5eb013dde128776 (patch) | |
| tree | 005bd7c0453e1d17ea2916064a2cea3204cc5e61 /target/arm | |
| parent | target/arm: Optimize MVE VDUP (diff) | |
| download | qemu-5cf525a8a68f5734feef8899d5eb013dde128776.tar.gz qemu-5cf525a8a68f5734feef8899d5eb013dde128776.tar.xz qemu-5cf525a8a68f5734feef8899d5eb013dde128776.zip | |
target/arm: Optimize MVE VMVN
Optimize the MVE VMVN insn by using TCG vector ops when possible.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210913095440.13462-9-peter.maydell@linaro.org
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/translate-mve.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c index 13de55242e..4583e22f21 100644 --- a/target/arm/translate-mve.c +++ b/target/arm/translate-mve.c @@ -769,7 +769,7 @@ static bool trans_VREV64(DisasContext *s, arg_1op *a) static bool trans_VMVN(DisasContext *s, arg_1op *a) { - return do_1op(s, a, gen_helper_mve_vmvn); + return do_1op_vec(s, a, gen_helper_mve_vmvn, tcg_gen_gvec_not); } static bool trans_VABS_fp(DisasContext *s, arg_1op *a) |