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| author | Richard Henderson | 2022-10-24 07:18:50 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-10-27 12:34:31 +0200 |
| commit | 65c123fdf577413a7d910e6b07c10e79d118041f (patch) | |
| tree | 6adee993e59fd3659d1b8f5d314d961aee93c400 /target/arm | |
| parent | target/arm: Implement FEAT_HAFDBS, access flag portion (diff) | |
| download | qemu-65c123fdf577413a7d910e6b07c10e79d118041f.tar.gz qemu-65c123fdf577413a7d910e6b07c10e79d118041f.tar.xz qemu-65c123fdf577413a7d910e6b07c10e79d118041f.zip | |
target/arm: Implement FEAT_HAFDBS, dirty bit portion
Perform the atomic update for hardware management of the dirty bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221024051851.3074715-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/cpu64.c | 2 | ||||
| -rw-r--r-- | target/arm/ptw.c | 16 |
2 files changed, 17 insertions, 1 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f2c3e41f5a..3d74f134f5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1165,7 +1165,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64mmfr0 = t; t = cpu->isar.id_aa64mmfr1; - t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 1); /* FEAT_HAFDBS, AF only */ + t = FIELD_DP64(t, ID_AA64MMFR1, HAFDBS, 2); /* FEAT_HAFDBS */ t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9941fa0ef9..a1f4ae654f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1445,6 +1445,22 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, goto do_fault; } } + + /* + * Dirty Bit. + * If HD is enabled, pre-emptively set/clear the appropriate AP/S2AP + * bit for writeback. The actual write protection test may still be + * overridden by tableattrs, to be merged below. + */ + if (param.hd + && extract64(descriptor, 51, 1) /* DBM */ + && access_type == MMU_DATA_STORE) { + if (regime_is_stage2(mmu_idx)) { + new_descriptor |= 1ull << 7; /* set S2AP[1] */ + } else { + new_descriptor &= ~(1ull << 7); /* clear AP[2] */ + } + } } /* |