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| author | Peter Maydell | 2020-11-19 22:56:00 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-12-10 12:44:55 +0100 |
| commit | 6a017acdf83e3bb6bd5e85289ca90b2ea3282b7e (patch) | |
| tree | a78244e3134cd9d987b4e495e118282d586b30d2 /target/arm | |
| parent | target/arm: Implement M-profile FPSCR_nzcvqc (diff) | |
| download | qemu-6a017acdf83e3bb6bd5e85289ca90b2ea3282b7e.tar.gz qemu-6a017acdf83e3bb6bd5e85289ca90b2ea3282b7e.tar.xz qemu-6a017acdf83e3bb6bd5e85289ca90b2ea3282b7e.zip | |
target/arm: Use new FPCR_NZCV_MASK constant
We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR
in the previous commit; use it in a couple of places in existing code,
where we're masking out everything except NZCV for the "load to Rt=15
sets CPSR.NZCV" special case.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-12-peter.maydell@linaro.org
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/translate-vfp.c.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index d698f3e1cd..cd8d5b4f28 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -744,7 +744,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, * helper call for the "VMRS to CPSR.NZCV" insn. */ tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); - tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); storefn(s, opaque, tmp); break; default: @@ -885,7 +885,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) case ARM_VFP_FPSCR: if (a->rt == 15) { tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); - tcg_gen_andi_i32(tmp, tmp, 0xf0000000); + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); } else { tmp = tcg_temp_new_i32(); gen_helper_vfp_get_fpscr(tmp, cpu_env); |