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| author | Peter Maydell | 2020-11-19 22:55:54 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-12-10 12:44:55 +0100 |
| commit | 6e21a013fbdf54960a079dccc90772bb622e28e8 (patch) | |
| tree | fe61490dd29e358be206973eec13dd354c8ff792 /target/arm | |
| parent | target/arm: Implement VSCCLRM insn (diff) | |
| download | qemu-6e21a013fbdf54960a079dccc90772bb622e28e8.tar.gz qemu-6e21a013fbdf54960a079dccc90772bb622e28e8.tar.xz qemu-6e21a013fbdf54960a079dccc90772bb622e28e8.zip | |
target/arm: Implement CLRM instruction
In v8.1M the new CLRM instruction allows zeroing an arbitrary set of
the general-purpose registers and APSR. Implement this.
The encoding is a subset of the LDMIA T2 encoding, using what would
be Rn=0b1111 (which UNDEFs for LDMIA).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-6-peter.maydell@linaro.org
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/t32.decode | 6 | ||||
| -rw-r--r-- | target/arm/translate.c | 38 |
2 files changed, 43 insertions, 1 deletions
diff --git a/target/arm/t32.decode b/target/arm/t32.decode index cfcc71bfb0..f045eb62c8 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -609,7 +609,11 @@ UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot STM_t32 1110 1000 10.0 .... ................ @ldstm i=1 b=0 STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1 -LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0 +{ + # Rn=15 UNDEFs for LDM; M-profile CLRM uses that encoding + CLRM 1110 1000 1001 1111 list:16 + LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0 +} LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1 &rfe !extern rn w pu diff --git a/target/arm/translate.c b/target/arm/translate.c index 9f2b6018a2..47a1a5739c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -7968,6 +7968,44 @@ static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a) return do_ldm(s, a, 1); } +static bool trans_CLRM(DisasContext *s, arg_CLRM *a) +{ + int i; + TCGv_i32 zero; + + if (!dc_isar_feature(aa32_m_sec_state, s)) { + return false; + } + + if (extract32(a->list, 13, 1)) { + return false; + } + + if (!a->list) { + /* UNPREDICTABLE; we choose to UNDEF */ + return false; + } + + zero = tcg_const_i32(0); + for (i = 0; i < 15; i++) { + if (extract32(a->list, i, 1)) { + /* Clear R[i] */ + tcg_gen_mov_i32(cpu_R[i], zero); + } + } + if (extract32(a->list, 15, 1)) { + /* + * Clear APSR (by calling the MSR helper with the same argument + * as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0) + */ + TCGv_i32 maskreg = tcg_const_i32(0xc << 8); + gen_helper_v7m_msr(cpu_env, maskreg, zero); + tcg_temp_free_i32(maskreg); + } + tcg_temp_free_i32(zero); + return true; +} + /* * Branch, branch with link */ |