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| author | Richard Henderson | 2022-10-24 07:18:40 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-10-27 11:27:23 +0200 |
| commit | 980a68925c8f19ae181c226af0776c0e3ddd0264 (patch) | |
| tree | f9c6329b52691b4842602a892f44f96d54d85010 /target/arm | |
| parent | target/arm: Add ptw_idx to S1Translate (diff) | |
| download | qemu-980a68925c8f19ae181c226af0776c0e3ddd0264.tar.gz qemu-980a68925c8f19ae181c226af0776c0e3ddd0264.tar.xz qemu-980a68925c8f19ae181c226af0776c0e3ddd0264.zip | |
target/arm: Add isar predicates for FEAT_HAFDBS
The MMFR1 field may indicate support for hardware update of
access flag alone, or access flag and dirty bit.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221024051851.3074715-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/cpu.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 09564d0393..9aeed3c848 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4152,6 +4152,16 @@ static inline bool isar_feature_aa64_e0pd(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, E0PD) != 0; } +static inline bool isar_feature_aa64_hafs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) != 0; +} + +static inline bool isar_feature_aa64_hdbs(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HAFDBS) >= 2; +} + static inline bool isar_feature_aa64_tts2uxn(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, XNX) != 0; |