diff options
| author | Emilio G. Cota | 2018-02-20 02:51:58 +0100 |
|---|---|---|
| committer | Richard Henderson | 2018-05-09 19:12:21 +0200 |
| commit | b542683d77b4f56cef0221b267c341616d87bce9 (patch) | |
| tree | de651b8d95bd698263970af7d0456e597d999f2b /target/arm | |
| parent | target/mips: avoid integer overflow in next_page PC check (diff) | |
| download | qemu-b542683d77b4f56cef0221b267c341616d87bce9.tar.gz qemu-b542683d77b4f56cef0221b267c341616d87bce9.tar.xz qemu-b542683d77b4f56cef0221b267c341616d87bce9.zip | |
translator: merge max_insns into DisasContextBase
While at it, use int for both num_insns and max_insns to make
sure we have same-type comparisons.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/translate-a64.c | 8 | ||||
| -rw-r--r-- | target/arm/translate.c | 9 |
2 files changed, 6 insertions, 11 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 6d49f30b4a..1e7c150514 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13224,8 +13224,8 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s) free_tmp_a64(s); } -static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, - CPUState *cpu, int max_insns) +static void aarch64_tr_init_disas_context(DisasContextBase *dcbase, + CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cpu->env_ptr; @@ -13288,11 +13288,9 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase, if (dc->ss_active) { bound = 1; } - max_insns = MIN(max_insns, bound); + dc->base.max_insns = MIN(dc->base.max_insns, bound); init_tmp_a64_array(dc); - - return max_insns; } static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0f6629f745..731cf327a1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -12243,8 +12243,7 @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s) return !thumb_insn_is_16bit(s, insn); } -static int arm_tr_init_disas_context(DisasContextBase *dcbase, - CPUState *cs, int max_insns) +static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *dc = container_of(dcbase, DisasContext, base); CPUARMState *env = cs->env_ptr; @@ -12305,14 +12304,14 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase, /* If architectural single step active, limit to 1. */ if (is_singlestepping(dc)) { - max_insns = 1; + dc->base.max_insns = 1; } /* ARM is a fixed-length ISA. Bound the number of insns to execute to those left on the page. */ if (!dc->thumb) { int bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; - max_insns = MIN(max_insns, bound); + dc->base.max_insns = MIN(dc->base.max_insns, bound); } cpu_F0s = tcg_temp_new_i32(); @@ -12323,8 +12322,6 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase, cpu_V1 = cpu_F1d; /* FIXME: cpu_M0 can probably be the same as cpu_V0. */ cpu_M0 = tcg_temp_new_i64(); - - return max_insns; } static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) |