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| author | Rémi Denis-Courmont | 2021-01-12 11:45:11 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-01-19 15:38:52 +0100 |
| commit | bc944d3a8b305029196a5e1406702a92fa0b94cf (patch) | |
| tree | 866ca1f7f3598f65de12eae98d81a22b384b4468 /target/arm | |
| parent | target/arm: enable Secure EL2 in max CPU (diff) | |
| download | qemu-bc944d3a8b305029196a5e1406702a92fa0b94cf.tar.gz qemu-bc944d3a8b305029196a5e1406702a92fa0b94cf.tar.xz qemu-bc944d3a8b305029196a5e1406702a92fa0b94cf.zip | |
target/arm: refactor vae1_tlbmask()
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-19-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/helper.c | 25 |
1 files changed, 11 insertions, 14 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index f3ee6d9808..d2ead3fcbd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4470,26 +4470,23 @@ static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, static int vae1_tlbmask(CPUARMState *env) { uint64_t hcr = arm_hcr_el2_eff(env); + uint16_t mask; if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { - uint16_t mask = ARMMMUIdxBit_E20_2 | - ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E20_0; - - if (arm_is_secure_below_el3(env)) { - mask >>= ARM_MMU_IDX_A_NS; - } - - return mask; - } else if (arm_is_secure_below_el3(env)) { - return ARMMMUIdxBit_SE10_1 | - ARMMMUIdxBit_SE10_1_PAN | - ARMMMUIdxBit_SE10_0; + mask = ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0; } else { - return ARMMMUIdxBit_E10_1 | + mask = ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | ARMMMUIdxBit_E10_0; } + + if (arm_is_secure_below_el3(env)) { + mask >>= ARM_MMU_IDX_A_NS; + } + + return mask; } /* Return 56 if TBI is enabled, 64 otherwise. */ |