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| author | Peter Maydell | 2020-11-19 22:55:51 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-12-10 12:44:55 +0100 |
| commit | cad8e2e3160dd10371552fce6cd8c6e171503e13 (patch) | |
| tree | bcde7749d9e1cf67fce6467318adbc61955e7462 /target/arm | |
| parent | hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault (diff) | |
| download | qemu-cad8e2e3160dd10371552fce6cd8c6e171503e13.tar.gz qemu-cad8e2e3160dd10371552fce6cd8c6e171503e13.tar.xz qemu-cad8e2e3160dd10371552fce6cd8c6e171503e13.zip | |
target/arm: Implement v8.1M PXN extension
In v8.1M the PXN architecture extension adds a new PXN bit to the
MPU_RLAR registers, which forbids execution of code in the region
from a privileged mode.
This is another feature which is just in the generic "in v8.1M" set
and has no ID register field indicating its presence.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-3-peter.maydell@linaro.org
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/helper.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index 38cd35c049..7b8bcd6903 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11754,6 +11754,11 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, } else { uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2); uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1); + bool pxn = false; + + if (arm_feature(env, ARM_FEATURE_V8_1M)) { + pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1); + } if (m_is_system_region(env, address)) { /* System space is always execute never */ @@ -11761,7 +11766,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, } *prot = simple_ap_to_rw_prot(env, mmu_idx, ap); - if (*prot && !xn) { + if (*prot && !xn && !(pxn && !is_user)) { *prot |= PAGE_EXEC; } /* We don't need to look the attribute up in the MAIR0/MAIR1 |