diff options
| author | Richard Henderson | 2022-05-01 07:49:51 +0200 |
|---|---|---|
| committer | Peter Maydell | 2022-05-05 10:35:51 +0200 |
| commit | cbe645856fb17ca0f2395fa4a75d80bdd0421614 (patch) | |
| tree | 9c277e44bef1b16fcc73669b28f70d89f84c3927 /target/arm | |
| parent | target/arm: Name CPState type (diff) | |
| download | qemu-cbe645856fb17ca0f2395fa4a75d80bdd0421614.tar.gz qemu-cbe645856fb17ca0f2395fa4a75d80bdd0421614.tar.xz qemu-cbe645856fb17ca0f2395fa4a75d80bdd0421614.zip | |
target/arm: Name CPSecureState type
Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable.
Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0
is handled in define_one_arm_cp_reg_with_opaque.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/cpregs.h | 7 | ||||
| -rw-r--r-- | target/arm/helper.c | 7 |
2 files changed, 9 insertions, 5 deletions
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 4179a8cdd5..73984549d2 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -131,10 +131,11 @@ typedef enum { * registered entry will only have one to identify whether the entry is secure * or non-secure. */ -enum { +typedef enum { + ARM_CP_SECSTATE_BOTH = 0, /* define one cpreg for each secstate */ ARM_CP_SECSTATE_S = (1 << 0), /* bit[0]: Secure state register */ ARM_CP_SECSTATE_NS = (1 << 1), /* bit[1]: Non-secure state register */ -}; +} CPSecureState; /* * Access rights: @@ -266,7 +267,7 @@ struct ARMCPRegInfo { /* Access rights: PL*_[RW] */ CPAccessRights access; /* Security state: ARM_CP_SECSTATE_* bits/values */ - int secure; + CPSecureState secure; /* * The opaque pointer passed to define_arm_cp_regs_with_opaque() when * this register was defined: can be used to hand data through to the diff --git a/target/arm/helper.c b/target/arm/helper.c index d560a6a6a9..50ad2e3e37 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8502,7 +8502,8 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) } static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, CPState state, int secstate, + void *opaque, CPState state, + CPSecureState secstate, int crm, int opc1, int opc2, const char *name) { @@ -8785,7 +8786,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, r->secure, crm, opc1, opc2, r->name); break; - default: + case ARM_CP_SECSTATE_BOTH: name = g_strdup_printf("%s_S", r->name); add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_S, @@ -8795,6 +8796,8 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->name); break; + default: + g_assert_not_reached(); } } else { /* AArch64 registers get mapped to non-secure instance |