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| author | Richard Henderson | 2021-03-09 16:53:04 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-03-12 13:40:10 +0100 |
| commit | e610906c56f98c76888d45beb7f579935dd61a70 (patch) | |
| tree | 9bd8b6d98ff5a0043b08aec02a1ea9f303417ce3 /target/arm | |
| parent | target/arm: Update CNTP for PREDDESC (diff) | |
| download | qemu-e610906c56f98c76888d45beb7f579935dd61a70.tar.gz qemu-e610906c56f98c76888d45beb7f579935dd61a70.tar.xz qemu-e610906c56f98c76888d45beb7f579935dd61a70.zip | |
target/arm: Update WHILE for PREDDESC
Since b64ee454a4a0, all predicate operations should be
using these field macros for predicates.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210309155305.11301-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/sve_helper.c | 4 | ||||
| -rw-r--r-- | target/arm/translate-sve.c | 7 |
2 files changed, 6 insertions, 5 deletions
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index a95bbece4f..6f4bc3a3cc 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -2850,8 +2850,8 @@ uint64_t HELPER(sve_cntp)(void *vn, void *vg, uint32_t pred_desc) uint32_t HELPER(sve_while)(void *vd, uint32_t count, uint32_t pred_desc) { - uintptr_t oprsz = extract32(pred_desc, 0, SIMD_OPRSZ_BITS) + 2; - intptr_t esz = extract32(pred_desc, SIMD_DATA_SHIFT, 2); + intptr_t oprsz = FIELD_EX32(pred_desc, PREDDESC, OPRSZ); + intptr_t esz = FIELD_EX32(pred_desc, PREDDESC, ESZ); uint64_t esz_mask = pred_esz_masks[esz]; ARMPredicateReg *d = vd; uint32_t flags; diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 722805cf99..2420cd741b 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3097,7 +3097,8 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a) TCGv_i64 op0, op1, t0, t1, tmax; TCGv_i32 t2, t3; TCGv_ptr ptr; - unsigned desc, vsz = vec_full_reg_size(s); + unsigned vsz = vec_full_reg_size(s); + unsigned desc = 0; TCGCond cond; if (!sve_access_check(s)) { @@ -3161,8 +3162,8 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a) /* Scale elements to bits. */ tcg_gen_shli_i32(t2, t2, a->esz); - desc = (vsz / 8) - 2; - desc = deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); + desc = FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); + desc = FIELD_DP32(desc, PREDDESC, ESZ, a->esz); t3 = tcg_const_i32(desc); ptr = tcg_temp_new_ptr(); |