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| author | Richard Henderson | 2021-06-14 01:21:01 +0200 |
|---|---|---|
| committer | Richard Henderson | 2021-06-29 19:04:57 +0200 |
| commit | ebdd503d4572cc446a9a61410755cc3b87e2d76f (patch) | |
| tree | 6895e30a1a6e5ffb5ed68b17cf3714303e0d08cf /target/arm | |
| parent | target/arm: Improve vector REV (diff) | |
| download | qemu-ebdd503d4572cc446a9a61410755cc3b87e2d76f.tar.gz qemu-ebdd503d4572cc446a9a61410755cc3b87e2d76f.tar.xz qemu-ebdd503d4572cc446a9a61410755cc3b87e2d76f.zip | |
target/arm: Improve REVSH
The new bswap flags can implement the semantics exactly.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/arm')
| -rw-r--r-- | target/arm/translate.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index 669b0be578..a0c6cfa902 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -354,9 +354,7 @@ void gen_rev16(TCGv_i32 dest, TCGv_i32 var) /* Byteswap low halfword and sign extend. */ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) { - tcg_gen_ext16u_i32(var, var); - tcg_gen_bswap16_i32(var, var, TCG_BSWAP_IZ | TCG_BSWAP_OZ); - tcg_gen_ext16s_i32(dest, var); + tcg_gen_bswap16_i32(var, var, TCG_BSWAP_OS); } /* Dual 16-bit add. Result placed in t0 and t1 is marked as dead. |