diff options
| author | Bastian Koppelmann | 2021-03-05 14:06:38 +0100 |
|---|---|---|
| committer | Bastian Koppelmann | 2021-03-14 14:49:01 +0100 |
| commit | a21993c7f98862823280d1eb6d3e93cf6267896f (patch) | |
| tree | 95cba878e0753b1816e70c6f5a47de812d0e0416 /target/hexagon | |
| parent | target/tricore: Fix imask OPC2_32_RRPW_IMASK for r3+1 == r2 (diff) | |
| download | qemu-a21993c7f98862823280d1eb6d3e93cf6267896f.tar.gz qemu-a21993c7f98862823280d1eb6d3e93cf6267896f.tar.xz qemu-a21993c7f98862823280d1eb6d3e93cf6267896f.zip | |
target/tricore: Fix OPC2_32_RRPW_EXTR for width=0
if width was 0 we would run into the assertion:
qemu-system-tricore: tcg/tcg-op.c:217: tcg_gen_sari_i32: Assertion `arg2 >= 0 && arg2 < 32' failed.o
The instruction manual specifies undefined behaviour for this case. So
we bring this in line with the golden Infineon simlator 'tsim', which
simply writes 0 to the result in case of width=0.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target/hexagon')
0 files changed, 0 insertions, 0 deletions