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| author | Helge Deller | 2020-08-27 13:10:32 +0200 |
|---|---|---|
| committer | Helge Deller | 2020-09-02 23:16:48 +0200 |
| commit | df5c6a50944697bf1373582dcea719697edbc9ed (patch) | |
| tree | 38f37da32b9da19345ca984e681531f8b6235e5e /target/hppa | |
| parent | seabios-hppa: Update SeaBIOS to hppa-qemu-5.2-2 tag (diff) | |
| download | qemu-df5c6a50944697bf1373582dcea719697edbc9ed.tar.gz qemu-df5c6a50944697bf1373582dcea719697edbc9ed.tar.xz qemu-df5c6a50944697bf1373582dcea719697edbc9ed.zip | |
hw/hppa: Make number of TLB and BTLB entries configurable
Until now the TLB size was fixed at 256 entries. To allow operating
systems to utilize more TLB entries in the future, we need to tell
firmware how many TLB entries we actually support in the emulation.
Firmware then reports this to the operating system via the
PDC_CACHE_INFO call.
This patch simply does the preparation to allow more TLB entries.
Signed-off-by: Helge Deller <deller@gmx.de>
Diffstat (limited to 'target/hppa')
| -rw-r--r-- | target/hppa/cpu.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 801a4fb1ba..fb6c59d075 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -196,9 +196,12 @@ struct CPUHPPAState { target_ureg shadow[7]; /* shadow registers */ /* ??? The number of entries isn't specified by the architecture. */ +#define HPPA_TLB_ENTRIES 256 +#define HPPA_BTLB_ENTRIES 0 + /* ??? Implement a unified itlb/dtlb for the moment. */ /* ??? We should use a more intelligent data structure. */ - hppa_tlb_entry tlb[256]; + hppa_tlb_entry tlb[HPPA_TLB_ENTRIES]; uint32_t tlb_last; }; |