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| author | Edgar E. Iglesias | 2018-04-16 21:03:01 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias | 2018-05-29 09:35:14 +0200 |
| commit | d2f004c3cdcb786303057683252112c3ff7b337e (patch) | |
| tree | 5b9c75b2975c2f595ac1da513c9af02bc9895be9 /target/microblaze/mmu.h | |
| parent | target-microblaze: mmu: Remove unused register state (diff) | |
| download | qemu-d2f004c3cdcb786303057683252112c3ff7b337e.tar.gz qemu-d2f004c3cdcb786303057683252112c3ff7b337e.tar.xz qemu-d2f004c3cdcb786303057683252112c3ff7b337e.zip | |
target-microblaze: mmu: Prepare for 64-bit addresses
Prepare for 64-bit addresses.
This makes no functional difference as the upper parts of
the 64-bit addresses are not yet reachable.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target/microblaze/mmu.h')
| -rw-r--r-- | target/microblaze/mmu.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index 624becfded..1714caf82e 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -28,7 +28,7 @@ #define RAM_TAG 0 /* Tag portion */ -#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */ +#define TLB_EPN_MASK MAKE_64BIT_MASK(10, 64 - 10) #define TLB_PAGESZ_MASK 0x00000380 #define TLB_PAGESZ(x) (((x) & 0x7) << 7) #define PAGESZ_1K 0 @@ -42,7 +42,7 @@ #define TLB_VALID 0x00000040 /* Entry is valid */ /* Data portion */ -#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */ +#define TLB_RPN_MASK MAKE_64BIT_MASK(10, 64 - 10) #define TLB_PERM_MASK 0x00000300 #define TLB_EX 0x00000200 /* Instruction execution allowed */ #define TLB_WR 0x00000100 /* Writes permitted */ @@ -63,7 +63,7 @@ struct microblaze_mmu { /* Data and tag brams. */ - uint32_t rams[2][TLB_ENTRIES]; + uint64_t rams[2][TLB_ENTRIES]; /* We keep a separate ram for the tids to avoid the 48 bit tag width. */ uint8_t tids[TLB_ENTRIES]; /* Control flops. */ |