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| author | Edgar E. Iglesias | 2018-04-14 17:59:29 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias | 2018-05-29 09:35:14 +0200 |
| commit | 0a22f8cf3ec1716865d635688fbfb31402c0ba7a (patch) | |
| tree | 96d7d48ecaf55af2f6debf9c3a3960b291418945 /target/microblaze/op_helper.c | |
| parent | target-microblaze: dec_msr: Fix MTS to FSR (diff) | |
| download | qemu-0a22f8cf3ec1716865d635688fbfb31402c0ba7a.tar.gz qemu-0a22f8cf3ec1716865d635688fbfb31402c0ba7a.tar.xz qemu-0a22f8cf3ec1716865d635688fbfb31402c0ba7a.zip | |
target-microblaze: Make special registers 64-bit
Extend special registers to 64-bits. This is in preparation for
MFSE/MTSE, moves to and from extended special registers.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target/microblaze/op_helper.c')
| -rw-r--r-- | target/microblaze/op_helper.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index f5e851e38d..4dc3aff84b 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -94,16 +94,17 @@ void helper_debug(CPUMBState *env) { int i; - qemu_log("PC=%8.8x\n", env->sregs[SR_PC]); - qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n", + qemu_log("PC=%" PRIx64 "\n", env->sregs[SR_PC]); + qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " + "debug[%x] imm=%x iflags=%x\n", env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], env->debug, env->imm, env->iflags); qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", env->btaken, env->btarget, (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", - (env->sregs[SR_MSR] & MSR_EIP), - (env->sregs[SR_MSR] & MSR_IE)); + (bool)(env->sregs[SR_MSR] & MSR_EIP), + (bool)(env->sregs[SR_MSR] & MSR_IE)); for (i = 0; i < 32; i++) { qemu_log("r%2.2d=%8.8x ", i, env->regs[i]); if ((i + 1) % 4 == 0) |