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| author | Philippe Mathieu-Daudé | 2021-01-10 22:44:59 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-01-14 17:13:54 +0100 |
| commit | fc63010e9bb9efa95221f2873edb2006a40d4b6c (patch) | |
| tree | 769b0e12d9ba6b615b82589d578186b82d1a745c /target/mips/cpu-defs.c.inc | |
| parent | target/mips: Remove CPU_R5900 definition (diff) | |
| download | qemu-fc63010e9bb9efa95221f2873edb2006a40d4b6c.tar.gz qemu-fc63010e9bb9efa95221f2873edb2006a40d4b6c.tar.xz qemu-fc63010e9bb9efa95221f2873edb2006a40d4b6c.zip | |
target/mips: Remove CPU_NANOMIPS32 definition
nanoMIPS not a CPU, but an ISA. The nanoMIPS ISA is already
defined as ISA_NANOMIPS32.
Remove this incorrect definition and update the single CPU
implementing it, the I7200.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210112210152.2072996-3-f4bug@amsat.org>
Diffstat (limited to 'target/mips/cpu-defs.c.inc')
| -rw-r--r-- | target/mips/cpu-defs.c.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index ba22ff4bcd..9f7bac8793 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -486,8 +486,8 @@ const mips_def_t mips_defs[] = .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | - ASE_MT, + .insn_flags = CPU_MIPS32R6 | ISA_NANOMIPS32 | + ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | ASE_MT, .mmu_type = MMU_TYPE_R4000, }, #if defined(TARGET_MIPS64) |