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| author | James Hogan | 2017-07-18 13:55:48 +0200 |
|---|---|---|
| committer | Yongbok Kim | 2017-07-20 23:42:26 +0200 |
| commit | 9658e4c342e6ae0d775101f8f6bb6efb16789af1 (patch) | |
| tree | 88365564def6e2ab588da96c24a9e14e9cedbae1 /target/mips/helper.c | |
| parent | target/mips: Fix TLBWI shadow flush for EHINV,XI,RI (diff) | |
| download | qemu-9658e4c342e6ae0d775101f8f6bb6efb16789af1.tar.gz qemu-9658e4c342e6ae0d775101f8f6bb6efb16789af1.tar.xz qemu-9658e4c342e6ae0d775101f8f6bb6efb16789af1.zip | |
target/mips: Weaken TLB flush on UX,SX,KX,ASID changes
There is no need to invalidate any shadow TLB entries when the ASID
changes or when access to one of the 64-bit segments has been disabled,
since doing so doesn't reveal to software whether any TLB entries have
been evicted into the shadow half of the TLB.
Therefore weaken the tlb flushes in these cases to only flush the QEMU
TLB.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Diffstat (limited to 'target/mips/helper.c')
| -rw-r--r-- | target/mips/helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/mips/helper.c b/target/mips/helper.c index 166f0d1243..11d6a86567 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -290,7 +290,7 @@ void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) #if defined(TARGET_MIPS64) if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { /* Access to at least one of the 64-bit segments has been disabled */ - cpu_mips_tlb_flush(env); + tlb_flush(CPU(mips_env_get_cpu(env))); } #endif if (env->CP0_Config3 & (1 << CP0C3_MT)) { |