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authorYongbok Kim2019-12-20 10:34:09 +0100
committerAleksandar Markovic2020-01-29 19:28:52 +0100
commitfeafe82cc2289a31b3e3f11dc76f3539ea22d670 (patch)
treeb22339b97d2f69b7e083df84b6899e42b2a2ba8c /target/mips/op_helper.c
parenthw/core/loader: Let load_elf() populate a field with CPU-specific flags (diff)
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target/mips: Amend CP0 WatchHi register implementation
WatchHi is extended by the field MemoryMapID with the GINVT instruction. The field is accessible by MTHC0/MFHC0 in 32-bit architectures and DMTC0/ DMFC0 in 64-bit architectures. Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1579883929-1517-4-git-send-email-aleksandar.markovic@rt-rk.com>
Diffstat (limited to 'target/mips/op_helper.c')
-rw-r--r--target/mips/op_helper.c23
1 files changed, 21 insertions, 2 deletions
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 79d44da6fa..7425a8868a 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -945,7 +945,12 @@ target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
{
- return env->CP0_WatchHi[sel];
+ return (int32_t) env->CP0_WatchHi[sel];
+}
+
+target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel)
+{
+ return env->CP0_WatchHi[sel] >> 32;
}
target_ulong helper_mfc0_debug(CPUMIPSState *env)
@@ -1016,6 +1021,11 @@ target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
return env->CP0_WatchLo[sel];
}
+target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel)
+{
+ return env->CP0_WatchHi[sel];
+}
+
target_ulong helper_dmfc0_saar(CPUMIPSState *env)
{
if ((env->CP0_SAARI & 0x3f) < 2) {
@@ -1869,11 +1879,20 @@ void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
{
- int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
+ uint64_t mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
+ if ((env->CP0_Config5 >> CP0C5_MI) & 1) {
+ mask |= 0xFFFFFFFF00000000ULL; /* MMID */
+ }
env->CP0_WatchHi[sel] = arg1 & mask;
env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
}
+void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
+{
+ env->CP0_WatchHi[sel] = ((uint64_t) (arg1) << 32) |
+ (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL);
+}
+
void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
{
target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;