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authorRichard Henderson2022-07-30 04:17:02 +0200
committerRichard Henderson2022-08-02 21:34:00 +0200
commitd44971e725c02e0656d2f53d4fb564f92e06aef7 (patch)
treebd997d6fd75f68109c166243284c14ad074e2034 /target/mips/tcg/sysemu/tlb_helper.c
parentMerge tag 'pull-migration-20220802c' of https://gitlab.com/dagrh/qemu into st... (diff)
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target/mips: Advance pc after semihosting exception
Delay generating the exception until after we know the insn length, and record that length in env->error_code. Fixes: 8ec7e3c53d4 ("target/mips: Use an exception for semihosting") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1126 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/mips/tcg/sysemu/tlb_helper.c')
-rw-r--r--target/mips/tcg/sysemu/tlb_helper.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c
index 57ffad2902..9d16859c0a 100644
--- a/target/mips/tcg/sysemu/tlb_helper.c
+++ b/target/mips/tcg/sysemu/tlb_helper.c
@@ -1056,6 +1056,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
case EXCP_SEMIHOST:
cs->exception_index = EXCP_NONE;
mips_semihosting(env);
+ env->active_tc.PC += env->error_code;
return;
case EXCP_DSS:
env->CP0_Debug |= 1 << CP0DB_DSS;