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| author | Philippe Mathieu-Daudé | 2021-04-13 10:47:10 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-05-02 16:49:35 +0200 |
| commit | a2b0a27d33e9b1079698cee04ff029a0555b5ea5 (patch) | |
| tree | 25d812498da93beddf8910ce957141066ce30daa /target/mips/tcg/tx79.decode | |
| parent | target/mips: Move CP0 helpers to sysemu/cp0.c (diff) | |
| download | qemu-a2b0a27d33e9b1079698cee04ff029a0555b5ea5.tar.gz qemu-a2b0a27d33e9b1079698cee04ff029a0555b5ea5.tar.xz qemu-a2b0a27d33e9b1079698cee04ff029a0555b5ea5.zip | |
target/mips: Move TCG source files under tcg/ sub directory
To ease maintenance, move all TCG specific files under the tcg/
sub-directory. Adapt the Meson machinery.
The following prototypes:
- mips_tcg_init()
- mips_cpu_do_unaligned_access()
- mips_cpu_do_transaction_failed()
can now be restricted to the "tcg-internal.h" header.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210428170410.479308-29-f4bug@amsat.org>
Diffstat (limited to 'target/mips/tcg/tx79.decode')
| -rw-r--r-- | target/mips/tcg/tx79.decode | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/target/mips/tcg/tx79.decode b/target/mips/tcg/tx79.decode new file mode 100644 index 0000000000..0f748b53a6 --- /dev/null +++ b/target/mips/tcg/tx79.decode @@ -0,0 +1,39 @@ +# Toshiba C790's instruction set +# +# Copyright (C) 2021 Philippe Mathieu-Daudé +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# Toshiba Appendix B C790-Specific Instruction Set Details + +########################################################################### +# Named attribute sets. These are used to make nice(er) names +# when creating helpers common to those for the individual +# instruction patterns. + +&rtype rs rt rd sa + +########################################################################### +# Named instruction formats. These are generally used to +# reduce the amount of duplication between instruction patterns. + +@rs_rt_rd ...... rs:5 rt:5 rd:5 ..... ...... &rtype sa=0 +@rt_rd ...... ..... rt:5 rd:5 ..... ...... &rtype rs=0 sa=0 +@rs ...... rs:5 ..... .......... ...... &rtype rt=0 rd=0 sa=0 +@rd ...... .......... rd:5 ..... ...... &rtype rs=0 rt=0 sa=0 + +########################################################################### + +MFHI1 011100 0000000000 ..... 00000 010000 @rd +MTHI1 011100 ..... 0000000000 00000 010001 @rs +MFLO1 011100 0000000000 ..... 00000 010010 @rd +MTLO1 011100 ..... 0000000000 00000 010011 @rs + +# MMI2 + +PCPYLD 011100 ..... ..... ..... 01110 001001 @rs_rt_rd + +# MMI3 + +PCPYUD 011100 ..... ..... ..... 01110 101001 @rs_rt_rd +PCPYH 011100 00000 ..... ..... 11011 101001 @rt_rd |